Use of ASICs has become widespread in the semiconductor industry as giving circuit design engineers a relatively high amount of circuit functionality in a relatively small package. In particular, ASICs are customizable integrated circuits that are customized to implement a circuit specified by a design engineer (a “user-designed circuit”). An example of an ASIC is a gate array or standard cell, which generally include a plurality of function blocks, each of which are predesigned and/or prefabricated to include a particular number, arrangement, and type of semiconductor devices, e.g., transistors. To customize an ASIC to implement a particular user-designed circuit specified by a design engineer, various connections are made among the semiconductor devices within the function block and/or various connections are made among function blocks (i.e., routing is customized).
Once ASICs are customized to implement a user-designed circuit, they must be initially tested to ensure that the user-designed circuit operates properly. Additionally, testing of the user-designed circuit after production and after the circuit has been incorporated into an end product is often necessary to determine if the circuit still operates properly. Tests must be able to detect faults, which are the results of defects (physical problems with the circuit, e.g., shorts, and/or improper circuit design), resulting in improper or unexpected circuit behavior.
Faults include “Stuck At Faults” (SAFs) and delay faults. SAFs occur when a particular connection in the circuit remains at (is “stuck” at) a logical low level or a logical high level regardless of what signals are applied to the circuit. (As used herein, “logical low” refers to a “0” signal, which is often a ground signal.
A “logical high” refers to a “1” signal, which is often a VDD signal.) Delay faults occur when the circuit is designed to accommodate a particular propagation time, but the circuit actually operates much slower than expected. For instance, if a circuit was designed with the belief that there would only be a 5 ns propagation time of a signal between a first point and a second point, but in operation the signal actually takes 15 ns to propagate from the first point to the second point, the circuit may not operate properly.
Well-designed tests of an integrated circuit will generally be able to detect most SAFs at the gate level (i.e., the conceptual circuit design level containing Boolean logic, flip-flops, etc.) by testing all connections between logic elements. In order to test all connections between logic elements, the tester needs to be able to (1) access the integrated circuit, (2) control, or set, the value at a particular connection and (3) be able to observe the value at the particular connection. For instance, in order to test the connection between point A and point B for Stuck At 0 Faults, the tester needs to be able to apply stimulus data that ought to place a logical high on the connection line, and then the tester needs to be able to observe the connection to see if and how the value changes as a result of the stimulus data.
One method of testing an integrated circuit that enjoys the most popularity among IC designers is “scan” testing, which will be described with reference to the block diagrams of FIGS. 1 and 1A. In FIG. 1, circuit 102 is generally composed of any number and arrangement of logic elements (e.g., Boolean logic gates, flip-flops, latches, etc.) and has input A and output B. Inputs A can be coupled directly to flip-flops 104 (via lines 114) or to other logic elements in logic 102. Likewise, outputs from flip-flops 104 can be coupled directly to outputs B (via lines 112), to other logic elements in logic 102, or directly to other flip-flop 104 inputs. Each flip-flop 104 contained in circuit 102 is coupled to a clock signal such as CLK1108 or CLK2109. The flip-flops 104, shown apart from the circuit 102 for illustrative purposes only, will each, upon receiving a triggering clock edge, store a value and hold the value on its respective output until a next triggering clock edge is received. Therefore the flip-flops of circuit 102 collectively represent the state of the circuit: at any time when the clocks are stopped, the flip-flops will maintain the state of the circuit.
By taking advantage of the state-machine nature of the circuit, the state of the circuit 102 can be controlled for test purposes by placing known values into the flip-flops 104. Similarly, the state of the circuit can also be observed by reading the values held in the flip-flops after the circuit has been run. In order to control and observe the values held in flip-flops 104 of the circuit 102, the flip-flops 104 are, in addition to their regular circuit connections represented by lines 112 and 114, coupled to one another in a daisy-chain fashion, i.e., the output of one flip-flop is coupled to the input of the next flip-flop, as generally shown in FIG. 1A. Furthermore, clock steering logic, such as multiplexer 111, is frequently inserted so that all testing and shifting can be effected with one clock signal.
To test logic circuit 102, external Integrated Circuit test equipment (“external IC tester”) must be manually connected to the circuit and controlled by a user. The external IC test equipment stops the regular “mission mode” operation of logic circuit 102 and shifts a series of stimulus values into flip-flops 104, via the daisy-chain, so that each flip-flop in logic circuit 102 has a known value. The external IC test equipment shifts the stimulus values into circuit 102 by applying the stimulus values one at a time to the input 106 of the first flip-flop in the daisy-chain and running the circuit clock 108 (coupled to the clock input of each flip-flop 104) to propagate the values through the daisy-chain. After the flip-flops 104 have each received a known test value, the external IC test equipment then exercises circuit 102 (runs normally) for a brief period, e.g., one clock cycle, and then stops circuit 102. The state of the circuit resulting from its being run is captured in flip-flops 104. The external IC test equipment then shifts the resulting values out of the flip-flops 104, by again running the clock 108 and reading the values at the output 110 of the last flip-flop in the daisy-chain.
More specifically, to implement scan-type testing, typically one of two techniques is used: mux-based scan or clock-based scan. “Mux-based scan” is the more commonly used technique and is described with reference to the block diagram of FIG. 2. Clock-based scan will be described with reference to FIG. 3.
As shown in FIG. 2, for each flip-flop 104n in the logic circuit 102, (where flip-flops 104 are shown apart from circuit 102 for illustrative purposes only) a 2-input multiplexer 212n is placed at the D-input of each respective flip-flop 104n. One input, e.g., the 0 input, for each multiplexer 212n receives the regular connection 114 from the logic 102 that would otherwise go directly into the D-input but for the multiplexer 212n. The second input, e.g., the 1 input, of each multiplexer 212n is coupled to the output of a flip-flop 104n+1, thereby daisy-chaining the flip-flops. As shown in FIG. 2, the Q-output of flip-flop 1042 is coupled to the 1-input of multiplexer 2121, and the Q-output of flip-flop 1041 would be coupled to another multiplexer 2120 (not shown). The 1-input to multiplexer 2122 would be received from the Q-output of flip-flop 1043 (not shown). A circuit clock line (CLK) 108 is coupled to each of the flip-flops 104n as it would be without inclusion of multiplexers 212n. A SHIFT signal 214 is coupled to the select input of each of the multiplexers 212n. When SHIFT 214 is a logical low, the circuit operates normally, as if the multiplexers were not present. Such normal circuit operation can be used for regular mission mode operation as well as for exercising circuitry during test modes. When SHIFT is a logical high, the circuit is placed in a “shift mode” of operation and test data (stimulus or result values) is shifted into or out of flip-flops 104n by application of a clock signal on CLK 108.
In FIG. 2, to test circuit 102, external IC test equipment is applied to control the SHIFT signal 214 and the signal on CLK 108. The external IC test equipment first places circuit 102 in shift mode by placing a logical high signal on SHIFT 214. The clock signal on CLK 108 is run in a controlled manner by the external IC test equipment to shift stimulus values into the flip-flops 104. Once stimulus values are in place, SHIFT 214 is brought to a logical low. The external IC test equipment then runs the clock signal on CLK 108 a limited number of clock cycles, e.g., one clock cycle. Resulting values are then captured in the flip-flops 104n by operation of the last clock edge in this test sequence, also sometimes referred to as a “capture clock.” SHIFT is then brought to a logical high, re-entering shift mode, and external IC test equipment applies a signal on CLK 108 to allow the captured data to be shifted out of the flip-flops 104n into external IC test equipment to be analyzed.
While the above testing method is useful as described for detecting SAFs, mux-based scan can also be used to test for delay faults. To do so, test data would be shifted into the flip-flops 104n as described above. Then external IC test equipment applies two clock edges—“a launch clock” and “a capture clock”—on CLK 108 with controlled timing between them. The “launch clock” is the clock edge that places the circuit in a state ready for test. In delay fault testing, the first clock edge that occurs after the stimulus data is finally positioned in flip-flops 104 is the launch clock, while in the SAF testing scenario described above, the launch clock would essentially be the last clock edge to occur in shift mode. The “capture clock” is the clock edge at which resulting values are captured in the flip-flops 104, and is similar in both delay fault and SAF testing. After the launch clock and the capture clock have been applied, external IC test equipment shifts resultant data out of the flip-flops 104n as described above. If the captured data does not correspond to that expected, then a delay fault may be detected.
Typically, there are many “design-for-test” rules (DFT rules) that have become generally known and used in designing user-designed circuits as a direct consequence of mux-based scan in order to avoid problems during testing. These DFT rules include the following:                Circuits should preferably not be designed to include falling-edge triggered flip-flops. Otherwise, some flip-flops would be clocked on the rising edge of the circuit clock, and some would be clocked on the falling edge. In such a situation, during a test data shift in, some of the flip-flops may not receive appropriate stimulus values and to avoid this situation extra test flip-flops may need to be included in the daisy-chain.        Clocks should only be designed to be coupled to clock pins and not to the D-input of a flip-flop or a gate that ultimately is coupled to the D-input of a flip-flop. Otherwise, setup and hold time violations may occur during test mode and the circuit will not reliably capture response values.        The Q-output of a flip-flop should not be directly or indirectly (e.g., through combinational logic or drivers) coupled to the clock input of another flip-flop (such as in a Johnson counter), as that clock-input will not be adequately controllable during testing. More generally, clock inputs throughout the circuit must be controllable for testing the circuit.        All gates through which the clock passes must also be controlled during testing to allow the clock to pass uninfluenced by other values during test value shifting. For instance, if the clock signal is applied to the first input of a 2-input AND-gate, where the AND-gate output is applied to the clock input of a flip-flop, then the second input to the AND-gate must be held to a logical high during a test value shift.        All asynchronous clear and reset pins must be gated so they can be prevented from interfering with shift mode.Other DFT rules are also commonly known. Many of these DFT rules are a direct result of the fact that testing, e.g., controlling and observing values using external IC test equipment, can only be done with static patterns (logical high and logical low values)—clock edge transitions can not be generated.        
Thus, the DFT rules, which have often developed as a result of the limitations of mux-based scan, have placed considerable limits on the design of the circuit, all to simply allow user intervention and testing of the circuit.
A second type of scan technique is “clock-based scan”, described with reference to the block diagram of FIG. 3. Rather than replacing each flip-flop in the logic circuit 102 with a mux/flip-flop combination as in mux-based scan, the flip-flops 104n in the logic design 102 are replaced with a dual interface flip-flop 304 shown in FIG. 3. Flip-flop 304 is composed of one flip-flop having two interfaces: one interface is shown in lower portion 310 and one interface is shown in the upper portion 312 of flip-flop 304. When placed in a circuit 102, the inputs and outputs (D, Q, CLK) of lower interface 310 are coupled to receive signals used for normal operation (mission mode). The inputs and outputs (TD, TQ) of upper interface 312 are coupled with the upper interface of other flip-flops 304 to form a daisy-chain, and TCLK is coupled to receive a test clock signal from an external IC test equipment, which can be distinct from the regular circuit clock (the “user clock”) coupled to CLK.
A signal input to SHIFT 314 indicates whether the upper interface or the lower interface should be active. When the signal coupled to the SHIFT input 314 is a logical low, the upper interface 312 maybe inactive while the lower interface 310 must be active. Thus, when the signal on SHIFT 314 is low, the circuit 102 behaves in mission mode. When the signal on SHIFT 314 is a logical high, the lower interface 310 must be inactive and the upper interface 312 must be active. Stimulus values are shifted into the respective flip-flops 304 via the daisy chained upper-interfaces 312, using external IC test equipment which controls the shift mode using TCLK. Once stimulus values are in place, the external IC test equipment will run the circuit in test mode for a controlled time period (i.e., SHIFT receives a logical low), after which SHIFT is again asserted high to enable captured values to be shifted out under control of TCLK. As will be understood by those of skill in the art, clock-based scan can easily mimic mux-based scan. As is also known in the art, device 304 maybe a latch having two interfaces (one for mission and test modes and one for shift mode) rather than a flip-flop.
Clock-based scan is advantageous over mux-based scan in that clock-based scan has fewer DFT rules associated with it. Since a separate interface and test clock are used for testing, most clock related DFT rules will no longer need to be followed when designing the underlying circuit. Nonetheless, clock-based scan tends to be more expensive than mux-based scan, causing it to be used less frequently than mux-based scan.
Thus, although external IC test equipment is widely used to test integrated circuits, these techniques are replete with limitations. For example, external IC test equipment must be physically attached to the circuit to perform testing. After the circuit has been completed and incorporated into a product, subsequent testing often becomes much more difficult. The circuit may be located in an area that is not easily accessible, such as on a satellite, in a hazardous materials area, etc.
In addition to requiring user involvement, existing testing techniques do not provide for at speed testing of circuits with multiple asynchronous clock domains.
Therefore, an ASIC design that inexpensively (in terms of real estate and other resources) implements remote and/or automated internal self-testing of a circuit implemented by the ASIC, permits testing of the circuit without the need for external equipment, allows at speed testing of the circuit subsequent to implementation into a product, or allows testing of a circuit with multiple asynchronous clock domains would represent an advancement in the art.